Standard mass-production is a well-known manufacturing concept. To make small quantities or even single items of a product according to user specifications at an affordable price, alternative agile production paradigms should be investigated and developed. The system presented in this article is based on a grid of cheap reconfigurable production units, called equiplets. A grid of these equiplets is capable to produce a variety of different products in parallel at an affordable price. The underlying agent-based software for this system is responsible for the agile manufacturing. An important aspect of this type of manufacturing is the transport of the products along the available equiplets. This transport of the products from equiplet to equiplet is quite different from standard production. Every product can have its own unique path along the equiplets. In this article several topologies are discussed and investigated. Also, the planning and scheduling in relation to the transport constraints is subject of this study. Some possibilities of realization are discussed and simulations are used to generate results with the focus on efficiency and usability for different topologies and layouts of the grid and its internal transport system. Closely related with this problem is the scheduling of the production in the grid. A discussion about the maximum achievable load on the production grid and its relation with the transport system is also included.
Abstract: Unlike manufacturing technology for semiconductors and printed circuit boards, the market for traditional micro assembly lacks a clear public roadmap. More agile manufacturing strategies are needed in an environment in which dealing with change becomes a rule instead of an exception. In this paper, an attempt is made to bring production with universal micro assembly cells to the next level. This is realised by placing a larger number of cells, called Equiplets, in a “Grid”. Equiplets are compact and low-cost manufacturing platforms that can be reconfigured to a broad number of applications. Benchmarking Equiplet production has shown reduced time to market and a smooth transition from R&D to Manufacturing. When higher production volumes are needed, more systems can be placed in parallel to meet the manufacturing demand. Costs of product design changes in the later stage of industrialisation have been reduced due to the modular production in grids, which allows the final design freeze to be postponed as late as possible. The need for invested capital is also pushed backwards accordingly. doi 10.1007/978-3-642-11598-1_32
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Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
