People counting is a challenging task with many applications. We propose a method with a fixed stereo camera that is based on projecting a template onto the depth image. The method was tested on a challenging outdoor dataset with good results and runs in real time.
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In this paper, we address the problem of people detection and tracking in crowded scenes using range cameras. We propose a new method for people detection and localisation based on the combination of background modelling and template matching. The method uses an adaptive background model in the range domain to characterise the scene without people. Then a 3D template is placed in possible people locations by projecting it in the background to reconstruct a range image that is most similar to the observed range image. We tested the method on a challenging outdoor dataset and compared it to two methods that each shares one characteristic with the proposed method: a similar template-based method that works in 2D and a well-known baseline method that works in the range domain. Our method performs significantly better, does not deteriorate in crowded environments and runs in real time.
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Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
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