Particle image velocimetry has been widely used in various sectors from the automotive to aviation, research, and development, energy, medical, turbines, reactors, electronics, education, refrigeration for flow characterization and investigation. In this study, articles examined in open literature containing the particle image velocimetry techniques are reviewed in terms of components, lasers, cameras, lenses, tracers, computers, synchronizers, and seeders. The results of the evaluation are categorized and explained within the tables and figures. It is anticipated that this paper will be a starting point for researchers willing to study in this area and industrial companies willing to include PIV experimenting in their portfolios. In addition, the study shows in detail the advantages and disadvantages of past and current technologies, which technologies in existing PIV laboratories can be renewed, and which components are used in the PIV laboratories to be installed.
Robots need sensors to operate properly. Using a single image sensor, various aspects of a robot operating in its environment can be measured or monitored. Over the past few years, image sensors have improved a lot: frame rate and resolution have increased, while prices have fallen. As a result, data output has increased and in a number of applications data transfer to a processing unit has become the limiting factor for performance. Local processing in the sensor is one way of reducing data transfer. A report on the Vision in Robotics and Mechatronics project
Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
