Robots need sensors to operate properly. Using a single image sensor, various aspects of a robot operating in its environment can be measured or monitored. Over the past few years, image sensors have improved a lot: frame rate and resolution have increased, while prices have fallen. As a result, data output has increased and in a number of applications data transfer to a processing unit has become the limiting factor for performance. Local processing in the sensor is one way of reducing data transfer. A report on the Vision in Robotics and Mechatronics project
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This study aims to understand how alternative tourism can contribute to the destination image of Palestine, given its negative image in the media. It proposes a framework for various destination image aspects and applies this framework in the context of alternative tourism in Palestine. It seeks to explore the key image formation factors, the perceived images of Palestine, and the post-visit behaviours of tourists who had engaged in alternative tourism in Palestine. This research contributes in fulfilling intriguing gaps in the Palestinian destination’s image literature, as well as the alternative tourism field that has emerged manifestly in Palestine. This study is exploratory in nature applying qualitative methodology by using open-ended questions in email interviews, and the interviews were analysed using thematic analysis. The empirical results proved that tourists who had visited Palestine and engaged in alternative tourism, had positive destination images, opposite to the ones portrayed in the media that show Palestine as a dangerous place to visit. Finally, this research provides academic and managerial implications.
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Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
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Many lithographically created optical components, such as photonic crystals, require the creation of periodically repeated structures [1]. The optical properties depend critically on the consistency of the shape and periodicity of the repeated structure. At the same time, the structure and its period may be similar to, or substantially below that of the optical diffraction limit, making inspection with optical microscopy difficult. Inspection tools must be able to scan an entire wafer (300 mm diameter), and identify wafers that fail to meet specifications rapidly. However, high resolution, and high throughput are often difficult to achieve simultaneously, and a compromise must be made. TeraNova is developing an optical inspection tool that can rapidly image features on wafers. Their product relies on (a) knowledge of what the features should be, and (b) a detailed and accurate model of light diffraction from the wafer surface. This combination allows deviations from features to be identified by modifying the model of the surface features until the calculated diffraction pattern matches the observed pattern. This form of microscopy—known as Fourier microscopy—has the potential to be very rapid and highly accurate. However, the solver, which calculates the wafer features from the diffraction pattern, must be very rapid and precise. To achieve this, a hardware solver will be implemented. The hardware solver must be combined with mechatronic tracking of the absolute wafer position, requiring the automatic identification of fiduciary markers. Finally, the problem of computer obsolescence in instrumentation (resulting in security weaknesses) will also be addressed by combining the digital hardware and software into a system-on-a-chip (SoC) to provide a powerful, yet secure operating environment for the microscope software.
Developing and realizing an innovative concept for the Active Aging campus in two years, where students, teachers, companies, residents of surrounding Campus neighborhoods will be invited to do exercise, sports, play, meet and participate. This includes, on the one hand, providing input with regard to a mobility-friendly design from an infrastructural perspective and, on the other hand, organizing activities that contribute to Healthy Aeging of the Zernike site and the city of Groningen. It is not only about having an Active Aging campus with an iconic image, but also about the process. In the process of realization, students, teachers, researchers, companies and residents from surrounding districts will be explicitly involved. This includes hardware (physical environment / infrastructure), software (social environment) and orgware (interaction between the two).
The increasing amount of electronic waste (e-waste) urgently requires the use of innovative solutions within the circular economy models in this industry. Sorting of e-waste in a proper manner are essential for the recovery of valuable materials and minimizing environmental problems. The conventional e-waste sorting models are time-consuming processes, which involve laborious manual classification of complex and diverse electronic components. Moreover, the sector is lacking in skilled labor, thus making automation in sorting procedures is an urgent necessity. The project “AdapSort: Adaptive AI for Sorting E-Waste” aims to develop an adaptable AI-based system for optimal and efficient e-waste sorting. The project combines deep learning object detection algorithms with open-world vision-language models to enable adaptive AI models that incorporate operator feedback as part of a continuous learning process. The project initiates with problem analysis, including use case definition, requirement specification, and collection of labeled image data. AI models will be trained and deployed on edge devices for real-time sorting and scalability. Then, the feasibility of developing adaptive AI models that capture the state-of-the-art open-world vision-language models will be investigated. The human-in-the-loop learning is an important feature of this phase, wherein the user is enabled to provide ongoing feedback about how to refine the model further. An interface will be constructed to enable human intervention to facilitate real-time improvement of classification accuracy and sorting of different items. Finally, the project will deliver a proof of concept for the AI-based sorter, validated through selected use cases in collaboration with industrial partners. By integrating AI with human feedback, this project aims to facilitate e-waste management and serve as a foundation for larger projects.
