Presentatie voor de 20e Nederlandse Testdag, m.m.v. Raymond Slot, Wiebe Wiersema, (HU), Christian Köppe (HAN, Arnhem), Sjaak Brinkkemper, Jan Martijn van der Werf (UU Utrecht). The Software Architecture of the Schiphol Group is taken as an example. Compliance checking of software rulescan be done with the Hogeschool Utrecht Software Architecture Compliance Checking Tool which is available at http://husacct.github.io/HUSACCT/
Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
Author Supplied: In the last decades, architecture has emerged as a discipline in the domain of Information Technology (IT). A well-accepted definition of architecture is from ISO/IEC 42010: "The fundamental organization of a system, embodied in its components, their relationships to each other and the environment, and the principles governing its design and evolution." Currently, many levels and types of architecture in the domain of IT have been defined. We have scoped our work to two types of architecture: enterprise architecture and software architecture. IT architecture work is demanding and challenging and includes, inter alia, identifying architectural significant requirements (functional and non-functional), designing and selecting solutions for these requirements, and ensuring that the solutions are implemented according to the architectural design. To reflect on the quality of architecture work, we have taken ISO/IEC 8402 as a starting point. It defines quality as "the totality of characteristics of an entity that bear on its ability to satisfy stated requirements". We consider architecture work to be of high quality, when it is effective; when it answers stated requirements. Although IT Architecture has been introduced in many organizations, the elaboration does not always proceed without problems. In the domain of enterprise architecture, most practices are still in the early stages of maturity with, for example, low scores on the focus areas ‘Development of architecture’ and ‘Monitoring’ (of the implementation activities). In the domain of software architecture, problems of the same kind are observed. For instance, architecture designs are frequently poor and incomplete, while architecture compliance checking is performed in practice on a limited scale only. With our work, we intend to contribute to the advancement of architecture in the domain of IT and the effectiveness of architecture work by means of the development and improvement of supporting instruments and tools. In line with this intention, the main research question of this thesis is: How can the effectiveness of IT architecture work be evaluated and improved?
