In this presented study, we measured in situ the uplink duty cycles of a smartphone for 5G NR and 4G LTE for a total of six use cases covering voice, video, and data applications. The duty cycles were assessed at ten positions near a 4G and 5G base-station site in Belgium. For Twitch, VoLTE, and WhatsApp, the duty cycles ranged between 4% and 22% in time, both for 4G and 5G. For 5G NR, these duty cycles resulted in a higher UL-allotted time due to time division duplexing at the 3.7 GHz frequency band. Ping showed median duty cycles of 2% for 5G NR and 50% for 4G LTE. FTP upload and iPerf resulted in duty cycles close to 100%.
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Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
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