Assigning gates to flights considering physical, operational, and temporal constraints is known as the Gate Assignment Problem. This article proposes the novelty of coupling a commercial stand and gate allocation software with an off-the-grid optimization algorithm. The software provides the assignment costs, verifies constraints and restrictions of an airport, and provides an initial allocation solution. The gate assignment problem was solved using a genetic algorithm. To improve the robustness of the allocation results, delays and early arrivals are predicted using a random forest regressor, a machine learning technique and in turn they are considered by the optimization algorithm. Weather data and schedules were obtained from Zurich International Airport. Results showed that the combination of the techniques result in more efficient and robust solutions with higher degree of applicability than the one possible with the sole use of them independently.
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The Gate Assignment Problem is tackled every day by different airports around the world. Assigning aircraft to gates has different associated costs. Conventional algorithms use mathematical models where only some assignment restrictions are considered. The approach proposed in this paper presents the novelty of coupling an optimization algorithm with an airport gate allocation simulator which provides the whole ensemble of assignment costs and restrictions. This approach allows using the simulator as the substitute for an assignment cost function in traditional algorithms. The proposed methodology starts with a feasible solution provided by the simulator. The framework proposed in this work improved the solution proposed by the simulator to a substantial extent.
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This study tackles the gate allocation problem (GAP) at the airport terminal, considering the current covid-19 pandemic restrictions. The GAP has been extensively studied by the research community in the last decades, as it represents a critical factor that determines an airport's capacity. Currently, the airport passenger terminal operations have been redesigned to be aligned and respect the covid-19 regulation worldwide. This provides operators with new challenges on how to handle the passengers inside the terminal. The purpose of this study is to come up with an efficient gate allocator that considers potential issues derived by the current pandemic, i.e., avoid overcrowded areas. A sim-opt approach has been developed where an evolutionary algorithm (EA) is used in combination with a dynamic passenger flow simulation model to find a feasible solution. The EA aims to find a (sub)optimal solution for the GAP, while the simulation model evaluates its efficiency and feasibility in a real-life scenario. To evaluate the potential of the Opt-Sim approach, it has been applied to a real airport case study.
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Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx BlockRAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080 × 1920) @103 fcps.
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When we make games, we have many implicit understandings of what constitutes an interaction from a player and what constitutes their goal for playing; however, in trying to build a method of understanding a simple interaction (such as finding a key to open a gate) numerous limitations of our understanding were revealed. This talk presents Prof. Mata Haggis-Burridge’s and Thomas Buijtenweg’s development of a new model for understanding video games and interactive media: the Journey to Content. The approach looks at core structural elements of digital games and breaks them down into constituents that help us to understand the player, content, gates, and keys. This model presents an unusual and revealing insight into both the structure of existing games and the assumptions that are usually sublimated by creators. Unlike high-level analysis models, such as the MDA Framework and Bartle’s Taxonomy of Players, the Journey to Content model examines the moment-to-moment interactions of players within both the system of the game and their wider societal context. Early application of the concepts from the model have shown that it has practical use for designers, and that it has potential for stimulating new game concepts. The model also has implications for metrics analysis and study/development of interactive systems beyond games. The talk also contains information about four types of ‘immersion’ in video games: systems immersion, spatial immersion, social/empathic immersion, and narrative immersion. It is discussed how these four types can be impacted in a variety of positive and negative ways by an individual change to a game. These four types of immersion are then compared and combined with the Journey To Content model to reveal new research questions.
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In the Netherlands and Europe, there exist approaches to refugee (re)settlement where asylum seekers face long waiting periods, in large-scale centres often isolated from Dutch society, with little-to-no opportunity to structure their day or participate in activities which bring meaning to their lives. These activities, which bring meaning people’s lives are termed occupations in the occupational therapy and occupation science literature. When the context hinders the opportunity to engage in these meaningful occupations, one experiences a situation of occupational injustice. These approaches taken in the Netherland and internationally creates the state of occupation injustice, this lack of ability to engage in meaningful activities, and this is turn has been documented to have negative effects on refugees health, well-being, identity and eventual inclusion in society.Parallel to these standard approaches in the Netherlands, are alternative approaches to refugee resettlement and integration. These alternatives are oftenbeing facilitated by charities, community-based organizations and citizen initiatives. Alternative programs currently aim to counter the government programs and focus on safe passages, for vulnerable populations, with an emphasis on early inclusion in society, community placement, sponsorship, and integration from the time of arrival. These alternative programs claim to address the issues of lack of meaningful engagement and isolation as currently seen in standard procedures, thereby claiming to improve integration, inclusion and wellbeing.This research aims to explore the lives and experiences of both the individuals living in, as well as the individuals facilitating these alternative programs. The research will explore how these programs are situated in and/or actively negotiating the broader context of refugee programs and policies in the Netherlands. This exploration will include the perspectives of the multiple actors involved, including service users and service providers, using a participatory methodology.Through exploring the perspectives on alternative programs through a participatory evaluation format, we are able to explore these programs as they are described, evaluated and experienced by theservices users themselves. This allows for a grounded understanding of the programs and their further potential.
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This report is the final report for the FPGA accelerated PID controller, part of the Distributed Control Systems project. This project runs within the Lectoraat Robotics and High Tech Mechatronics of Fontys Hogeschool Engineering Eindhoven. The Lectoraat has the goal to develop applicable knowledge to support education and industry. This knowledge is acquired with projects run in conjunction with the industry. The report will go into detail for the software designed for this project, not the hardware design. This report is intended for follow up students working on the Distributed Control Systems project. Within this report the assumption is made that the reader is at least familiar with the terms EtherCAT, FPGA, Linux and PID controllers. However for each part a small basic introduction is included. For readers looking for the accomplishments in this project, the results are in chapter six. Following are short descriptions of the chapters in this report. The first chapter will give a short introduction to the project. It talks about why the project was conceived, where the project was done and what the expected end result is. The second chapter, the problem definition, talks about how the project has been defined, what is included and what is not and how the customer expects the final product to function and look like. The third chapter details the methodology used during this project. All the research preformed for this project will be described in the forth chapter. This chapter goes into the research into the Xilinx Zynq 7000 chip, Beckhoff's EtherCAT system, how the Serial Peripheral Interface works and how a PID controller functions. Following in chapter five the design is expanded upon. First the toolchain for building for the Zynq chip is explained. This is followed by and explanation of the different software parts that have been designed. Finally chapters six and seven provide the results and the conclusions and recommendations for this project.
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